Job Description

Designation

Technical Lead

No. of Positions

1

Experience

4.5-8 Years

Skill (Primary)

Technical Skills (ERS)-VLSI-Verification Methodology-UVM

Qualification

B-Tech

Expected Date of Closure

01-Jun-2023

Job Family

Engineering (Engineering - VLSI)

Employee Group

Business Line FT

Job

VLSI Verification Lead

(Posting).

Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment.
Experience in ASIC design/verification related field in IP, Subsystem or SOC level
Experience in writing System Verilog and/or System C models for simulation
Working experience in writing UVM models, checkers, and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus
Compose test plan and validation vectors to ensure functional completeness
Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification
Excellent communication skills (both written and oral)
Strong problem-solving skills (1.) Prepare and own detailed verification Plan including test strategy, TB architecture, methodologies to be followed, corner case scenarios, test coverage requirements etc (2.) Mentoring and guiding the team in solving tech. issues (3.) Allocating and tracking tasks (per schedule), CR or risk tracking, support PM in effective project management, coordination of weekly and other team meetings (4.) Conduct test scenarios\' identification sessions and come up with a complete set of test plans and critical review of verification artifacts (5.) To prepare test plans for the module or interface owned by self and Coding of test cases as per test plans documented and functional simulation, debugging and fixing

HCL Technologies