Job Description

As a Principal ASIC Design Engineer and a senior Project Coordinator specializing in advanced node technology, you will spearhead the entire chip design process independently, from conceptualization to submission, leveraging your extensive expertise in Synopsys tools and collaboration with TSMC foundries. With over 20 years of experience in the semiconductor industry, your role will be pivotal in driving innovation and excellence in ASIC chip design at the forefront of technology, specifically focusing on 1nm to 3nm nodes. The entire project lifecycle, from architecture definition to RTL design, physical implementation, verification, and submission to fabrication foundries as TSMC. This position requires a deep knowledge and hands on practice of architecture, SOC, RTL design, programming languages such as C++ and Perl, and extensive experience with FPGA, IP, DSP, and UVM methodologies.Key Responsibilities: * End-to-End Project Leadership:

• Take full Responsibility and accountability of complex ASIC chip design projects, from initial architecture definition to final submission, demonstrating exceptional leadership and autonomy.
• Utilize your advanced understanding of Synopsys tools and methodologies to guide every aspect of the design process, ensuring efficiency, quality, and timely delivery.
• Innovative Design Methodologies:

• Develop and implement cutting-edge design methodologies tailored for 1nm to 3nm technology nodes, pushing the boundaries of innovation and performance in ASIC chip design.
• Employ sophisticated techniques for architecture exploration, SOC integration, RTL design, and physical implementation, optimizing for power, performance, and area (PPA) metrics.
• Technical Mastery and Mentorship:

• Showcase your unparalleled expertise in ASIC design, architecture, and verification, serving as a mentor to junior engineers and imparting decades of industry knowledge.
• Leverage your deep understanding of programming languages such as C++, Perl, and TCL to develop advanced automation scripts and tools, streamlining design flows and enhancing productivity.
• Foundry Collaboration and Strategic Partnerships:

• Forge strong partnerships with TSMC foundries, leveraging your extensive experience and insights to optimize design strategies, mitigate risks, and ensure successful tape-out and production.

Key Qualifications & Experience:

• Bachelor\'s or Master\'s degree in Electrical Engineering or related field, with over 20 years of hands-on experience in ASIC chip design, specifically focusing on advanced node technologies.
• Extensive expertise in Synopsys design tools and TSMC fabrication processes, with a proven track record of successful chip tape-outs and production at 1nm to 3nm nodes.
• Demonstrated ability to work independently and drive projects from inception to completion, showcasing exceptional problem-solving skills, attention to detail, and time management.
• Exceptional communication and leadership abilities, with a history of mentoring and guiding cross-functional teams to achieve ambitious design goals.

Preferred Skills:

• In-depth knowledge of physical design methodologies, timing closure techniques, and DFT strategies for advanced technology nodes.
• Proficiency in MATLAB for digital signal processing algorithm development and system-level simulation.
• Familiarity with emerging technologies and trends in the semiconductor industry, with a passion for continuous learning and innovation.

Note: This role requires a seasoned professional with over two decades of experience in ASIC chip design, specializing in advanced node technologies. The successful candidate will demonstrate a strong track record of individual leadership and innovation, coupled with exceptional technical proficiency in Synopsys tools and TSMC fabrication processes, shaping the future of semiconductor design.RequirementsJob Type: Full-timeSchedule:

• Day shift
• Monday to Friday

Ability to commute/relocate:

• Vancouver, BC : reliably commute or plan to relocate before starting work (required)

Education:

• PHD Degree (preferred)

Experience:

• synopsys
• ASIC Design
• Semiconductors

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