Job Description

and RequirementsASIC Physical Design Methodology Engineer, Sr. Staff
We are looking for an ASIC Physical Design Methodology Engineer to join the Digital Methodology Core Team (MCT). In this position, you will be expected to lead and oversee the integration, and continuous management of methodologies designed by this Core Team into Silicon IP teams. This is a matrix position where leading with influence and trust is highly prized. You will be a successful candidate in this role if you enjoy a breadth of technical understanding with a willingness to drive results while assessing relative risks on quality. This role will require strong verbal and written communication skills.
You are expected to have demonstrated previous experience balancing technical and leadership roles in at least two aspects of ASIC development covering anything from Front-End Development (RTL and Verification) to Back-End Development (PNR). You are also expected to have strong systems-level thinking to judge workflows and processes and make recommendations for improvement. You are an ideal candidate if you have previous specialization in at least two of the following areas but candidates with experience in multiple areas will be highly preferred:

• Lint/CDC
• ATPG/DFT
• Static Timing Analysis and timing budgeting
• Synthesis
• Place and Route
• Physical verification

Key job responsibilities

• Manage and mentor a team of MCT engineers supporting Silicon IP teams by integrating Methodologies into their development infrastructures and showing successful results
• Synthesize goals and milestones from senior leadership and MCT engineers to create plans and roadmaps using MBOs (Management by Objectives)
• Provide quarterly assessment of workflows and results, and make recommendations to the MCT team for improvement
• Hold regular cross-functional meetings to connect the MCT team with the Silicon IP teams, and maintain judicious notes to track status and report completion rates
• Assist in logistical and technical tasks as necessary

Qualifications

• Bachelor\'s/Master\'s degree in electrical or computer engineering and computer science
• 10+ years of experience running Front-End and Back-End Synthesis in advanced technology nodes, and using state-of-the-art EDA tools such as DC, ICC2, FC (Fusion Compiler)
• 5+ years of experience writing code in RTL for multi-clock designs, and with a strong understanding of Clock-Domain-Crossing (CDC) principles
• 5+ years of experience driving designs through EDA tools such as TetraMax, SpyGlass, VC SpyGlass, Z01X, TCM (Fishtail), PrimePower and VCS
• Familiarity with Functional Verification, including understanding of Assertions and Coverage
• Strong experience writing in RTL, TCL, Perl, and/or Python
• Understanding of Machine Learning Concepts and AI

Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world\'s broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.At Synopsys, we\'re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we\'re powering it all with the world\'s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected: Join ourSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryR&D Engineering

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