Job Description

Since 1992, Ciena has been driven by a relentless pursuit of network innovation. We believe in a network that grows smarter, more agile, and more responsive every day. This means that when you digitally interact in your world - picking up the phone, streaming video, texting a friend or loved one - your interactions are being enabled by Ciena technologies. Ciena makes your social / entertainment / business existence REAL.

No candidate will meet every single desired qualification. If your experience looks a little different from what we've identified below and you think you can bring value to the role, we'd love to learn more about you!

What will you do at Ciena as a Senior Digital Verification Engineer?

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a senior digital verification engineer will be to propose and implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.

As a senior digital verification engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects

You are held responsible for the complete and thorough validation of one or more architectural functional blocks by using an appropriate combination of simulation, formal and coverage methods

You are expected the create the verification, functional coverage and formal verification test plans

You are accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable

You will perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer

You are expected to report on status updates on a regular basis

What technical experience and personal skills are required for this role?

Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level

A highly motivated self-starter, able to work independently, while being a team player

Ability to methodically solve complex technical problems

Excellent organization, written and oral (English) communication skills

Proficiency above the intermediate level with use of System Verilog, UVM, SVA, and simulators from major vendors.

Proven ability in determining appropriate and comprehensive digital verification and coverage strategies

What additional assets can help me in this role?

Experience with formal verification methods

Experience in DSP and/or Forward Error Correction

Experience with using Jira for bug tracking and GIT for source code management and revision tracking

Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++

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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.