Job Description

Social networking, machine learning, and big data analytics demand ever-increasing network connectivity. RANOVUS, with operations in Ottawa, Canada, Nuremberg, Germany, and San Jose, USA, is a solution provider for the next generation data center infrastructures. We aim to deliver advanced technology that minimizes environmental impact through lower power dissipation. Working with world class fabrication partners, RANOVUS is the leader in the application of unique new technologies to fiber-optic communications products for data-centers.

Role Overview

We are seeking a Full Time Silicon Photonics Layout Designer to develop high-quality physical layouts for advanced photonic integrated circuits. The ideal candidate has strong experience using Cadence layout tools and a solid understanding of LVS/DRC flows for photonic designs. You will work closely with photonic device engineers, circuit designers, and process teams to translate schematics and specifications into manufacturable layouts for silicon photonics platforms.

Responsibilities

Create and maintain photonic layouts using Cadence (Virtuoso) and foundry PDKs. Implement waveguide routing, passive and electro-optic devices (rings, MZIs, couplers, modulators, detectors). Ensure layout compliance with foundry design rules (DRC) and perform LVS between schematic and layout. Debug and resolve DRC/LVS issues, including photonic-specific connectivity and hierarchy challenges. Integrate optical and electrical components in compact, manufacturable floorplans. Collaborate with design, modeling, and process teams to optimize layouts for performance, yield, and reliability. Prepare tape-out-ready GDS files and support signoff flows. Develop and improve layout methodologies, templates, and automation where applicable. Document layout guidelines and contribute to best practices for PIC design.

Qualifications

Bachelor's or master's degree in electrical engineering, Photonics, Physics, or a related field. 3+ years of experience in IC or photonic layout design. Strong proficiency with Cadence Virtuoso for layout. Hands-on experience running and debugging DRC and LVS. Familiarity with silicon photonics components and layouts (waveguides, rings, MZIs, grating couplers, heaters, PN junctions). Understanding of hierarchical layout, parameterized cells (PCells), and foundry PDK usage. Experience with mixed photonic/electrical layouts is a plus. Ability to interpret schematics, netlists, and design specifications. Strong attention to detail and ability to manage complex layouts across large designs.

Nice to Have

Experience with photonic LVS frameworks or custom connectivity checks. Scripting experience (Python, SKILL, MATLAB) for layout automation. Familiarity with multiple foundries or photonics PDKs (e.g., GF, TSMC, IME, Tower Jazz). Experience supporting silicon photonics tape-outs and post-silicon debug.



This role offers the opportunity to work on cutting-edge silicon photonics technology and contribute directly to next-generation optical systems.