Job Description

Overview:
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences--from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges--striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Responsibilities:
THE PERSON:
The ideal candidate would be someone who enjoys working in fast paced environments with emphasis on learning and problem solving. The CIT team designs and verifies cutting edge communication protocol IPs and sub-systems based on the UCIe and UALink standards. As part of the verification team, the candidate would be responsible for developing and maintaining DV flows and methodologies with a new emphasis on Automation, AI, Scalability, and Performance. A working knowledge of verification methodologies (UVM, Constrained Random Verification, Formal Verification) is an asset.
The CIT organization has great talent diversity from all over the globe and closely works with other teams. Our management fosters and encourages continuous technical innovation to showcase successes and facilitate continuous career development.
KEY RESPONSIBILITIES:

• Code line setup, build flow setup, Design/DV automation setup, Regression and Coverage optimization using LSF and cron, Perforce and GitHub
• Adapting UVM TB and DV flows to support emulation and post-silicon activities.
• Driving technical innovation to improve AMD's capabilities in IP validation/verification, including tool and script development, technical and procedural methodology improvement, and various internal and cross-functional technical initiatives.
• Working closely with supporting teams in design, diagnostics, emulation, firmware to ensure readiness for first silicon arrival, enablement of IP functionality and debug of critical features.

PREFERRED EXPERIENCE:

• DV planning for Metric Driven Verification and TB architecture.
• Deep knowledge of DV infrastructure, Make flow and other automation flows, shell, Perl, python, ruby.
• Knowledge of serial communication protocols in a plus.
• Experience with using AI/Machine Learning tools is a plus.
• Prior experience with System Verilog HVL and UVM methodology is a plus
• Familiarity with emulation and post-Si validation is a plus.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Vancouver, BC
#LI-SL3 Qualifications:
Benefits offered are described: .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Skills Required