Overview:
Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Senior Principal Engineering Lead / Manager to join our PCI-Express team in Montreal, Canada. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
The Senior Principal Engineering Lead/Manager must be a charismatic team leader and capable of hands-on engineering contributor/role model for RTL Design and Logic Verification activities. The successful candidate will be reporting to the Director of Engineering for Rambus SoftIP developments related to PCI-Express products. The candidate will be joining a team to work on cutting edge memory and silicon IP technology shaping the future of data centers and high-performance systems.
For this full-time position, Rambus offers a flexible work environment, embracing a hybrid approach. We encourage employees to spend an average of at least three days per week working onsite, allowing for two days of remote work
Responsibilities:
Contribute to product architecture definition, RTL logic development/code, and design team lead/management
Contribute/supervise development of test plans, tests and verification infrastructure for complex Block level / IP / Sub-system.
Qualifications:
Master's degree in Electronics Engineering, Electrical Engineering, or Computer Engineering
10-15+ years of logic design & verification experience
Fluency with Verilog/SystemVerilog language, SVA assertions, and use of System Verilog Functional Coverage.
Demonstrated experience with RTL logic synthesis, timing analysis, LINT checking, and CDC/RDC clock/reset-domain checking tools.
Experience with HVL-based verification and SV & OVM/UVM methods.
Some experience / awareness with PCI-Express protocols/implementations is a must.
Demonstrated team / people leadership skills/experience.
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