Job Description

Company: Qualcomm Canada ULC

Job Area: Engineering Group, Engineering Group
ASICS Engineering

General Summary:

Before there were smartphones or smart cities, before autonomous cars or 360 virtual reality videos, there was our technology. Headquartered in San Diego, for over 30 years Qualcomm's inventions have inspired others to make the impossible, possible. From 5G to artificial intelligence, IoT to automotive and extended reality applications, Qualcomm is inventing the technologies of an intelligently connected future, spearheading research efforts for the next global wireless standard, and collaborating with industry leaders in the wireless value chain to make this future a commercial reality.

We are searching for ASIC Design, Design Verification, and Implementation Engineers to be part of the Qualcomm Markham, Canada team developing hardware for Qualcomm Snapdragon processors to start innovating with them as early as January 2023.

When applying, you can specify which technical track(s) you would like to be considered for. By applying here, you are expressing interest in one of our many Qualcomm engineering positions. It is important to note that this is not a job posting for a specific role. We will review resumes on an ongoing basis, and a recruiter may reach out to you.

Job Overview

Multiple teams developing several technologies are hiring at our Markham, Ontario site:

• Compute/AI IP Team: Do you ever wonder when will connected devices become thinking devices? Be a part of the team working on AI/ML technology that will bring "Cognition" to all connected devices: That means devices that don't just think, but instinctively react to their surroundings.
• Display Processing IP Team: Be member of a team that develop the Next Generation Display Processing Units (DPUs) that are key to delivering vivid and stunning visual experiences in the mobile, compute, automotive and IoT markets.
• Low Power AI/Audio Processing IP Team: Perhaps you are an ASIC Engineer interested in developing world-class audio/ AI solutions

Minimum Qualifications

• Graduating with a bachelor's or master's degree in computer engineering, computer science, electrical engineering, or a related field no later than July 2023.
• 1+ years' experience with ASIC design, verification, or related work experience.

Successful candidates will have experience in one or more of the following Software Engineering technical tracks:

ASIC DESIGN

• Experience with cache control and/or video processing function design/verification
• Practiced design knowledge working with several of the following

• Clock domain crossing and Reset architecture
• FIFOs implementation/integration
• Bus implementation/verification techniques
• Memory selection and control
• High speed and low power design optimization
• Bus interface protocols (APB, AHB, AXI)
• Experience with several of the following

• Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
• Design rule and CDC checking (SVA assertions, Spyglass, 0-in)
• Model development (SystemC, or C++)
• RTL to gates synthesis (Synopsys DCG or Cadence Genus)
• Power analysis tools (CLP, Power Artist, PTPX, Power Compiler, PowerPro)
• Timing analysis tools (Primetime)
• Scripting languages (PERL, Python, TCL, C, etc.)

DESIGN VERIFICATION

• Good working experience with C/C++
• Strong knowledge of Object-Oriented Programming (OOP) concepts
• Hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC
• Hardware description languages (HDL): Verilog and SystemVerilog
• Knowledgeable in one or more of the following disciplines is preferred: Display (Pixel processing/composition/compression, MIPI DSI, DisplayPort, HDMI etc.), Bus/interconnect (AHB, AXI)
• Strong knowledge of digital circuits and event-driven simulators
• Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make
• ASIC Verification, Matlab C, Multicore System-On-Chip (SoC), Perl Programming, Simulation Software

IMPLEMENTATION

• Experience implementing designs Synthesis and closing with Static Timing Analysis
• Experience with High-speed/Low power ASIC design within a Unix environment
• Experience with clock domain crossing techniques and tools
• Experience with the following design tools / specifications:

• ASIC design and simulation tool sets (Synopsys/Cadence Mentor - DC, Genus, Fusion Compiler, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre, etc.)
• Working knowledge of UPF specification
• Design rule check (Spyglass, etc.)
• Formal verification (Formality, LEC, etc.)
• Power analysis and simulation
• Scripting languages (TCL, Python, Perl, C, etc.)
• Knowledge of bus interface protocols (APB, AHB, AXI)
• Working knowledge of UPF specification

Minimum Qualifications: . Bachelor's degree in Science, Engineering, or related field.

Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to

Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm's toll-free number found for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.

Qualcomm is an equal opportunity employer and supports workforce diversity.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

If you would like more information about this role, please contact .