Job Description

Location:

Toronto, Canada

Type:

Full Time

Travel:

Up to 10%

Overview:

Movellus Circuits Inc. is seeking a motivated and skilled ASIC Design Engineer to join our growing engineering team. This role offers an exciting opportunity to contribute to the physical realization of high-performance digital integrated circuits. The ideal candidate will possess a solid understanding of the ASIC implementation flow, with practical experience in RTL design (SystemVerilog), synthesis, place and route (PNR), and static timing analysis (STA). You will work collaboratively with senior engineers on challenging projects, playing a key role in bringing innovative digital designs to silicon.

Responsibilities:

Participate in RTL design and development using SystemVerilog. Contribute to the RTL synthesis process, including constraint generation and optimization. Drive and participate in the place and route (PNR) process, working closely with physical design methodologies and tools. Perform static timing analysis (STA) at various stages of the design flow to ensure timing closure. Work closely with RTL designers to resolve timing violations and implement necessary design changes. Contribute to power analysis and optimization efforts throughout the implementation flow. Assist in the generation and validation of timing constraints (SDC). Analyze synthesis, PNR, and STA reports to identify and resolve potential issues. Document implementation strategies, analysis results, and best practices. Collaborate effectively with cross-functional teams, including architects, RTL engineers, verification engineers.

Qualifications:

Bachelor's or Master's degree in Electrical Engineering or a related field. Minimum 2 years of relevant experience in ASIC implementation. Strong understanding of digital logic design principles and RTL development using SystemVerilog. Solid knowledge of the complete ASIC implementation flow from RTL to GDSII, including synthesis, place and route, static timing analysis, LVS/DRC. Hands-on experience with industry-standard EDA tools for synthesis, PNR, and STA, EMIR (e.g., Synopsys Design Compiler/ICC2/Custom Compiler, Cadence Genus/Innovus/Virtuoso, PrimeTime, Redhawk). Familiarity with timing constraint generation (SDC). Basic understanding of power analysis and optimization techniques in the context of implementation. Knowledge of scripting languages such as Python or TCL for automation is a plus. Strong analytical and problem-solving skills. Excellent communication and teamwork abilities.


Forward your resume directly to: careers@movellus.com