Job Description

and Requirements

Job Responsibilities

• Coordinate Mixed-Signal model development and methodology
• Coordinate Mixed-Signal verification, such as logic equivalency check, power analysis, and digital-analog simulation, with cross-functional teams
• Create timing model of custom mixed-signal circuits
• Identify and refine circuit design to achieve optimal power, area, and performance targets.
• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
• Oversee physical layout to minimize the effect of parasitic, device stress, and process variation.
• Present simulation data for peer and customer review.
• Document design features and test plans.
• Consult on the electrical characterization of your circuit within the IP product.

Job Requirements

• PhD with 2+ years, or MSc with 5+ years of analog IC design experience.
• In depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
• Experience with FinFET technologies is a plus.
• Experience with Mixed-Signal design methodology, including analog circuit modeling and digital-analog simulation methodology
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Detailed design experience with at least one, and familiarity with several other DDR or SerDes sub-circuits:

• receive equalizers, samplers, voltage/current-mode drivers, serializers, de-serializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
• Aware of ESD issues (i.e. circuit techniques, layout).
• Familiarity with custom digital design (i.e. high-speed logic paths).
• Knowledge of design for reliability (i.e. EM, IR, aging, etc.).
• Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.).
• Experience with tools for schematic entry, physical layout, and design verification.
• Hands-on experience with physical layout of high-speed circuits is a plus.
• Knowledge of SPICE simulators and simulation methods.
• Familiarity with Liberty timing model and static timing analysis
• Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
• Good communication and documentation skills.

Hire Type

Employee

Job Category

Engineering

Job Subcategory

Analog Design

Synopsys